Sample — to Hold-Mode Specifications

The switching from sample to hold mode is accompanied by transients that appear in the output. The time it takes for these transients to settle within a given error bound is called the settling time, similar to the corresponding sample-mode

Sample - to Hold-Mode Specifications

End point = P2



Gain error = 1 — tan в

Start point = P1


specification discussed in the preceding subsection. This non­ideal behavior is shown in Fig. 3. Another nonideal effect is also presented in Fig. 3 and is called the pedestal error. This error appears as an offset in the output signal and is due to charge injected from the sampling switch, which could be dependent on the input signal, implying nonlinearity.

Aperture time is another important specification and is de­fined as the amount of time it takes for the sampling switch to open. This is attributed to the finite slope of the clock and a gradual transition of the sampling switch from a low-imped — ance (closed) to a high-impedance (opened) state. The signal stored at the output is a function of the aperture delay ta, the analog delay tda of the signal through the sample-and-hold cir­cuit, and the digital delay tdd of the clock signal that turns off the switch. It can be ultimately characterized as shown in Fig. 4 by an effective aperture time teff. The analog delay is caused by the frequency response of the sample-and-hold cir­cuit, and the digital delay is produced by any logic in the path of the external clock to the switch. The aperture jitter is the variation in the hold signal delay. In some applications, such as analog-to-digital data conversion, a constant delay in the sampling time is not important. However, aperture jitter could be extremely damaging, adding significant noise to the output signal and effectively lowering the resolution of the system.

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