Level of Design Abstraction

A design can be described in different levels of abstraction, as shown in Fig. 1.

• Architecture level (also called behavioral level). At this level, the designer has the freedom to choose different algorithms to implement a design (for instance, different digital filtering or edge detection algorithms). The em­phasis is on input-output relations. Different implemen­tations for the same function can be considered. For in­stance, for a given function, one can chose between two logic implementations: sequential and parallel combina­tional (arithmetic adder, comparator or multiplier being good examples).

• Register transfer level (RTL). At this stage, the design is specified at the level of transfers among registers. Thus, the variables correspond to generalized registers, such as

 Figure 1. The abstraction levels of a logic design.

shifters, counters, registers, memories, and flip-flops. The operations correspond to transfers between registers and logical, arithmetical and other combinational opera­tions on single or several registers. Examples of opera­tions on a single register are shift left, shift right, shift cyclically, add one, subtract one, clear, set, negate. An example of more general register-transfer operations is A ^ B + C, which adds the contents of registers B and C and transfers the result to register A. A register-trans – fer description specifies the structure and timing of oper­ations in more detail but still allows for transformations of data path, control unit, or both. The transformations will allow improved timing, lower design cost, lower power consumption, or easier circuit test.

• Logic level (gate level). At this level every individual flip – flop and logic bit is specified. The timing is partially fixed to the accuracy of clock pulses. The (multioutput) Bool­ean functions with certain number of inputs, outputs, and certain fixed functionality are specified by the user or obtained by automatic transformations from a regis – ter-transfer level description. These functions are speci­fied as logic equations, decision diagrams, arrays of cubes, netlists, or some hardware description language (HDL) descriptions. They can be optimized for area, speed, testability, number of components, cost of compo­nents, or power consumption, but the general mac­ropulses of the algorithm’s execution cannot be changed.

• Physical level. At this level a generic, technology-inde­pendent logic function is mapped to a specific technol­ogy—such as electronically programmable logic devices (EPLD), complex programmable logic devices (CPLD), field programmable gate arrays (FPGA), standard cells, custom designs, application specific integrated circuits (ASIC), read only memory (ROM), random access mem­ory (RAM), microprocessor, microcontroller, standard small scale integration (SSI)/medium scale integration (MSI)/large scale integration (LSI) components, or any combinations of these. Specific logic gates, logic blocks, or larger design entities have been thus defined and are next placed in a two-dimensional area (on a chip or board) and routed (interconnected).