IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS

If one starts with the basic ideal model for a sample-and-hold circuit, there are various ways to implement a switch and a capacitor in either discrete or monolithic forms. The interface between this model and the input signal or adjacent system blocks implies the usage of additional circuitry. There is also added complexity from dealing with different circuit nonideal­ities, an increase in operating speed, or a decrease in power consumption. The following subsections embrace this gradual approach from a basic model to a more complex structure, which provides an implementation that is close to real life. A variety of topologies and implementations is presented includ­ing open – and closed-loop, bipolar, and MOS-based, as well as current-mode circuits.

Open-Loop Sample-and-Hold Circuits

The simplest voltage-mode sample-and-hold circuit requires only two elements: a switch and a capacitor, as shown in Fig. 6 (1-3). The switch is controlled by a clock signal ф that is turned on and off each sample period. When the switch is on, the input voltage appears on the capacitor, and the circuit is actually in track mode. When the switch is turned off, the signal voltage at that instance is sampled on the capacitor, which holds the voltage constant until the next track phase. Although this ideally implements the desired sample-and – hold function using only two elements, the difficulty in realiz­ing an ideal switch severely limits the performance of such a design. Real switches are implemented using MOS or bipolar transistors or diode bridges, each of which has its own idio­syncrasies. This subsection will primarily focus on the use of MOS switches, while circuits utilizing bipolar transistors or diodes will be discussed in the following subsection.

A MOS transistor deviates from an ideal switch in several ways, the most obvious of which is in terms of on-resistance. When the MOS switch is turned on, it typically will have a low drain-to-source voltage (VDS) and a high gate-to-source voltage (Vos) [re-type MOS assuming (NMOS), opposite polar­ity for p-type MOS (PMOS)], causing it to operate in the tri – ode or nonsaturation region, where the drain-to-source cur­rent (Ids) is given by (4)

W

Another limitation of the MOS switch is charge injection and clock feedthrough, which are sometimes used inter­changeably to describe two effects that occur when the switch is turned off. When the transistor is on, charge collects under the gate of the transistor to form the channel from drain to source. When the switch is turned off, this charge exits the channel primarily to the drain and source, with the propor­tional split depending on speed of the clock transition and the impedance seen by the charge in each direction (6). The part of the charge that exits toward the sampling capacitor will cause the capacitor voltage to drop slightly (assuming an NMOS transistor with negative channel charge) from its im­mediately previous value. This would only create a constant pedestal error in the sample-and-hold circuit output if the packet of charge were always the same, but unfortunately this is not the case. The channel charge is approximately given by

: CoxWL(Vgs – Vt )

which reveals that, if the gate of the switch is tied to a con­stant supply voltage while turned on, then the channel charge will be signal dependent. In reality, this signal dependence of the injected charge is a major source of nonlinearity in the sample-and-hold circuit.

The second effect, often termed clock feedthrough, is caused by the MOS overlap capacitance between the gate and source or drain connected to the sampling capacitor. As the gate volt­age is dropping from a high on-voltage to a low off-voltage, the transistor actually shuts off when the gate is approximately a threshold voltage above the source or drain voltage. As the gate voltage continues to fall further, the voltage step is ca­pacitively coupled onto the sampling capacitor through the MOS overlap capacitance, causing the voltage on the sam­pling capacitor to change.

(W/L vs. 2W/L) of the series switch device

reduced by driving the gate with a bootstrapped version of the input signal, which makes the effects independent of signal to first order, just as in the case of switch on-resistance. The use of a full CMOS switch rather than only a single NMOS or a single PMOS device also gives a very rough cancellation of these effects. The NMOS device will inject negative channel charge onto the sampling capacitor, while the PMOS switch will inject positive channel charge. Similarly, the charge cou­pled through the overlap capacitances will also be in opposing directions. Unfortunately, these cancellations do not hold as the input is varied over its input range and so give little benefit.

Dummy-switch cancellation is another technique that can be used, though generally with limited effectiveness, to re­duce charge injection and clock feedthrough. As shown in Fig. 7, a dummy-switch device with half the gate area of the main switch is placed on the capacitor side of the sampling switch and is clocked with an inverted version of the sampling signal ф. Thus, during acquisition, the main switch is on and the dummy switch is off. At the sampling instant, the dummy switch is turned on, causing it to pull charge from the sam­pling capacitor to form the channel under its gate. This charge approximately cancels that injected by the main switch, assuming roughly half of the main switch charge was injected toward the capacitor.

IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS

The simple sample-and-hold circuit using a MOS switch can also experience input signal feedthrough during the hold mode due to the MOS overlap capacitances, especially when sampling high-speed inputs. When the circuit is in hold mode, the MOS gate will be pulled to the low supply voltage (assum­ing an NMOS switch), typically by a digital gate’s output. The digital gate will have a finite, nonzero resistance from its out­put to the low supply voltage, yielding an effective circuit such as that shown in Fig. 8. Analysis of this circuit reveals a nonzero transfer function from the input to the sampled output node, causing the feedthrough. Care must be taken during the design process to characterize the level of

feed­through that occurs and keep it sufficiently low through a low-resistance gate drive or more elaborate design modifica­tions.

IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS

Vin

(a) Basic schematic

IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS

(c) Hold mode, clock high

IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS

(b) Track (sample) mode, clock low

Figure 15. Sample-and-hold circuit where the hold­ing capacitor is connected in series between input and output; (a) detailed schematic with TN1, TN2, TP1, TP2 as switches, and input-output buffering; (b) sim­plified schematic during track mode; (c) simplified schematic during hold mode.

are n-p-n devices that function as series switches for steer­ing bias currents. Transistors TP1 and TP2 are p-n-p devices and work in either linear region or are turned off. For simplic­ity, it is assumed that the input and output buffers have unity gain. When the clock signal is low, transistor TN2 is turned off, and transistors TN1 and TN3 are turned on. Current I1 [generated by the current source as shown in Fig. 15(a)] flows entirely through resistor Rb1, which is designed such that the voltage drop on it, IRb1, turns off transistor TP1 (p-n-p type). Also, current I2 [generated by a current source as shown in Fig. 15(a)] flows through transistor TP2 (p-n-p type), which is biased in the linear region. Removing all transistors that are turned off, the schematic can be simplified as in Fig. 15(b). The voltage Vr2 shown on this figure can be expressed as

Vr2 = Vbe>TP2 + VR = VTln i? b2 (10)

1S, TP2 eTP2

where Vbe, TP2 is the base-emitter voltage of transistor TP2, VT is the thermal voltage, IS, TP2 is a constant current related to transistor TP2, and /8TP2 is the forward gain factor for transis­tor TP2. In other words, voltage Vr2 is independent of the in­put signal and is equal to the sum of the base-emitter voltage of transistor TP2 and the voltage drop across resistor Rb2. The voltage on the capacitor is V^ = Vin — Vr2, which is basically a shifted version of the input. The output voltage Vout is reset to Vr2 during this track or sample phase. When the clock sig­nal goes high transistors TN1 and TN3 turn off and TN2 turns on. Current I1 is steered to flow entirely through resis­tor Rb2, which is designed in a similar fashion as Rb1 such that the voltage drop on it, IRb2, turns off transistor TP2. The sche­matic, again, can be simplified as in Fig. 15(c). The input buffer provides some current Ib, which flows through transis­tor TP1 biasing it in the linear region. Vr1 can be also ex­pressed as in Eq. (10)

Vri = Vbe>TP1 + VB = VT ln jb – + —i? bl (11)

S, TP1 eTP1

with similar meanings applied to transistor TP1. The output voltage becomes

Vout = Vr1 – VChold I sampled = Vr1 + Vr2 – Vin I sampled (12)

It is worth mentioning that the output voltage holds a value of the input sampled when the clock goes high, and it is reset to Vr2 when the clock goes back to the low state. This puts an additional bandwidth requirement on the output buffer, which needs to settle more than the full range of the input signal. Also, assuming unity gain buffers, as stated initially, the output is a shifted version of the input taken with oppo­site sign. To achieve a perfect copy of the sampled input, a differential topology should be employed (to eliminate the shift) and either the input or output buffer should have a neg­ative gain. Since there is no true track mode at the output, one could consider the voltage on the capacitor as a function of the input when clock is low, and derive the equivalent ‘‘on’’ switch resistance. However, this requires taking into account

supply

Vin

Vo,

Clock

Figure 17. Diode-bridge-based sample-and-hold circuit with buff­ering and clamping to the output voltage.

IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS

kTLTLn

Ш

V,

supply

the design of the buffers and the parasitic effects of bipolar devices, which becomes rather involved.

The most common high-speed sample-and-hold circuits em­ploy semiconductor diode bridges. The switching times for semiconductor diodes are inversely proportional to the cutoff frequency characteristic to a given bipolar or bipolar CMOS process. Also the ‘‘on’’ resistance for these devices is very low compared to MOS-based switches. For a given current and reasonable sizes, the transconductance of bipolar transistors is significantly higher than that for their MOS counterparts. Since semiconductor diodes can be considered as bipolar de­vices with the base shorted to the collector, their ‘‘on’’ resis­tance is Rswitch = 1/gm = VT/I, where VT is the thermal voltage and I is the bias current flowing through the diode. The small ‘‘on’’ resistance and short switching times make the diode – bridge-based sample-and-hold circuits attractive for very – high-speed applications. Figure 16 presents such a basic sam – ple-and-hold circuit without input and output buffering. The switch is implemented using a diode bridge and two switched current sources. When the clock is low, the switched current sources do not generate any current and present a very high impedance at their output such that the diodes turn off

IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS

The voltage at nodes A and B during the track mode is input dependent. However, during hold mode these voltages change to some value independent of the input, and this change couples to the output node through the diode D2 and D3 junction capacitance, creating nonlinearity. This ef­fect can be virtually eliminated during the hold mode by clamping nodes A and B to a value dependent on the input sample. This creates a constant voltage change at these nodes from track to hold, and consequently, a constant perturbation of the held voltage, which results in offset but no nonlinearity. Figure 17 presents a circuit that performs the described clamping operation and includes input and output buffers that are assumed to have unity gain. When the clock signal is high, transistor T2 is turned off and current I2 flows through the diode bridge, generating a low-resistance path between the input and the holding capacitor Chold. This is the track mode when the voltage on Chold and the output voltage are following the input voltage. When the clock goes low, during the hold mode, transistor T1 turns off and transistor T2 turns on, bypassing the diode bridge. Current I3 is necessary to clamp the voltage at node B to Vin|sampled + VonD6. Meanwhile, node A is clamped to Vin|sampled — Von, D5. So the voltage at nodes A and B changes from track to hold by — Von, D1 — Von/D5 and Von, D3 + VonD6, respectively. These Von voltages are dependent on the diode sizes and bias current [Von = VT ln(Ib/IS)] so the coupling from nodes A and B to the voltage on Chold through the junction capacitance of diodes D2 and D3 is signal inde­pendent. Also, during the track mode diodes D5 and D6 are turned off since the output voltage follows the input and the voltages at node A and B are Vin + VonD1 and Vin — VonD4, re­spectively. It is important to note that the range of the input signal is limited to keep the diodes and current

It is worth mentioning that gm2 and gm1 are physically differ­ent elements and their mismatches as well as nonlinearity impact the performance of this sample-and-hold circuit. Also, the speed of the circuit depends largely on the operational amplifier settling time.

Real-life implementations of the current-mode sample-and – hold circuits described so far include usually more elaborate structures that are targeted at cancelling parasitic effects. Some of them employ differential topologies or improvements related to the finite output impedance of MOS transistors. Other structures employ more sophisticated clocking schemes or feedback to cancel charge-injection errors. Furthermore, closed-loop architectures must deal with stability issues that come into play as a trade-off regarding the accuracy (in the case of discrete-time feedback as in Fig. 28) or the speed (for the continuous-time feedback as in Fig. 29) of the circuit. Al­though there are advantages in using current-mode sample – and-hold circuits particularly regarding operating speed, their widespread usage was hampered by the need of voltage – to-current and current-to-voltage conversions as well as im­plementation difficulties when higher accuracy is required.

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