Hardware description languages (HDLs) such as the Very High Speed Integrated Circuit Hardware Description Lan­
guage (VHDL) and Verilog are commonly used to specify the logic of a reconfigurable system. Descriptions in these languages have the advantage of being vendor neutral, so the same description can be synthesized for different tar­gets such as different FPGA devices, different FPGA ven­dors, and ASICs. For this reason, these languages are often the target language for higher level tools that offer higher levels of abstraction.

Module generators and libraries are commonly deployed to promote reuse. For example, vendors such as Altera and Xilinx have parameterized libraries of components that can be used in a design. These libraries are generated so that a circuit optimized for the particular application can be produced. As an example, a parameterized floating point library might allow the wordlength of the exponent and mantissa to be specified as well as whether denormalized numbers are supported. The module generator then gener­ates a netlist or VHDL-based floating point adder that can be included in a design.

A high level language can be directly mapped to a netlist or HDL. As an example, Luk and Page described a simple compilation process (8, 49) from a high level language with explicit parallel extensions to a register transfer language (RTL) description. Parallel execution of statements is im­plemented via parallel processes, and these can commu­nicate via channels through which a single-word message can be passed. Variables in the user program are mapped to registers, all expressions are implemented as combina­tional logic, and multiplexers are used in the case a reg­ister has multiple sources. A datapath that matches the dataflow graph of the input source description is gener­ated using this strategy. The clocking scheme employed is a global, synchronous one, and a convention that each as­signment takes exactly one clock cycle is followed. A start signal is used to feed the clock and to enable each register that corresponds to a variable, and a finish signal is gen­erated for the assignment in the following clock cycle. To execute statements sequentially, the start and finish sig­nals of adjacent statements are simply connected together, creating a one-hot distributed control scheme. Conditional statements and loops are formed by asserting one of sev­eral possible start signals that correspond to alternative basic blocks in a program. Completion ofconditional or loop constructs and synchronization of parallel blocks are im­plemented by combining relevant finish signals using the appropriate combinatorial logic. An example showing the translation of a simple code fragment to control and data­path is shown in Fig. 8.

Commercial tools that can compile standard program­ming languages such as Java, C, or C++ [e. g., (49)] are avail­able. Examples include Handel-C from Celoxica (50) and Catapult C from Mentor Graphics (51). The use of tradi­tional programming languages improves productivity as low level details are handled by the compiler. This is anal­ogous to C versus assembly language for software devel­opment. Another difference with potentially large implica­tion is that, using these tools, software developers can also design reconfigurable computing applications. Domain — specific languages such as MATLAB/Simulink (52) offer even greater improvements in productivity because they are interactive, include a large library of primitive rou­tines and toolkits, and have good graphing capabilities. Indeed, many designs for communications and signal pro­cessing are first prototyped in MATLAB and then con­verted to other languages for implementation. Tools such as the MATCH compiler (53) and Xilinx System Generator can translate a subset of MATLAB/Simulink directly to an FPGA design.

The availability of embedded operating systems such as Linux for microprocessors on an FPGA provides a fa­miliar software development environment for program­mers, greatly facilitating program development through the availability of a large range of open-source libraries as well as high quality development tools. Such tools can greatly speed up the development time and improve the quality of embedded systems. Hardware/software codesign tools such as Altera’s Nios II C-to-Hardware acceleration compiler enable time-critical functions in a C program to be converted to a hardware accelerator that is tightly coupled to a microprocessor within the FPGA (54).

Issues developing with the mapping of algorithms to hardware are more generally discussed by Isshiki and Dai (55), who focus on the differences between implementing bit-serial versus bit-parallel modules (e. g., adders and mul­tipliers) on FPGA architectures. Although latency is larger for bit-serial modules, the reduction in area frequently makes area-time products significantly lower for such im­plementations. More specifically, such advantages as the following can be obtained: 1) For bit-parallel modules, the I/O pin limitation is a major problem, and the large size of the module cluster can result in unused space and un­derutilized logic resources; 2) bit-serial modules are easier to partition as cell-to-cell connections are sparse and do not cause I/O problems; and 3) high fanout nets can impair routability of bit-parallel modules. Leong and Leong (56) generalized further with a design methodology that can translate a dataflow description with signals of different wordlengths to a digit serial design.

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