Monthly Archives: April 2014

Superconducting Materials for Electric Machines

Classes of Materials. Superconductors divide themselves into two major groups: the low-Tc and the high-Tc materials. The low-Tc superconductors (LTSs), the earlier ones, are industrial materials with high performance in terms of current capacity under high fields (1 T—5 T, Fig. 2). However, they operate in general only at temperatures near 4.2 K, which require a complex but well-controlled cryogenic system. The most common low-Tc superconducting multifilamentary composites use niobium titanium (NbTi) with typical cost of about 1 $/kAm to 2 $/kAm. This figure of merit, the cost of 1 m of wire carrying 1 kA, enables comparisons between materials. The compound niobium tin (Nb3Sn) is only used for very high-field applications (> 8 T) and is less used for electric machines. Its use is more complicated than that of NbTi, due to the long thermal treatments required after winding it, and its cost is higher (5 $/kAm to 10 $/kA m).

High-Tc superconductors (HTSs), assuming similar costs and performance to those of NbTi, will lead to a reduction in cryogenic costs (capital and especially operating costs), but the main advantage is the improvement in the stability of the superconducting state, which leads to higher reliability. At 20 K the specific heats are 200 times higher than at 4 K. The specific heat, being the amount of heat input necessary to raise the temperature, represents the materials inherent brake on temperature rise. HTSs are thus less sensitive to thermal disturbances.

Even with the large research effort focused on HTSs, these materials have not yet achieved the state of development stage of NbTi. HTSs are very complex anisotropic ceramic materials, difficult to fabricate in a conventional wire or cable. Intrinsically brittle, they are sensitive to mechanical stresses, and their transport properties under fields are still much poorer than those of NbTi (Fig. 2), except for highly oriented, essentially epitaxial films. They are also very expensive materials, and the current price is the main barrier to their
economic development. Their cost must be lowered to 10 $/kA m to be competitive (4). At present it is nearly 50 times higher.

There are two main routes to fabricate HTS wires. The more advanced one is the (powder-in-tube) (PIT) technique (5,6) based on bismuth-compound filaments embedded in a silver or silver alloy matrix (Fig. 2). Lengths of Bi-PIT tapes as long as 1 km are produced routinely by several companies throughout the world, and their typical critical current densities are shown in Fig. 2. Still higher critical current densities are obtained on small samples (Jc = 760 MA/m2 at 77 K, 0 T; Je & 250 MA/m2). Some specialists think nevertheless that the limits have almost been reached. The pure silver matrix unfortunately is not suitable for ac applications, due to the high ac coupling losses, and new PIT wires are under development for ac applications (5) (silver alloys, resistive barriers, etc.).

The second route consists of so-called coated conductors (7) and has much potential. Yttrium compounds are deposited in thick films (a few micrometers) on industrial flexible textured metallic substrates through a buffer layer. Very good performance has been obtained with these coated conductors, but only for short lengths. The engineering current density (overall current density including substrate) is large in liquid nitrogen (on the order of 200 megamperes per square meter at 77 K at present), and its decrease under field is small. A lot of difficulties must be overcome to fabricate long, high-performance coated conductors, and there is now no low-cost industrial deposition technique. High quality Y superconductor bulk pellets, up to 100 mm in diameter (8), have been processed, and they can be used in some special machines (hysteresis, reluctance, trapped-field, etc.).

(Fig. 3). As shown in Fig. 3, this minimum work increases rapidly at low temperatures. In order to take into account the real cycle and the imperfections of the thermodynamic transformations, this ratio should be divided by the efficiency factor of the refrigeration system:

Ac losses. One of the most spectacular properties of a superconductor is its absence of resistive losses. This is true, however, only for non-time-varying electromagnetic quantities (dc conditions). As soon as the magnetic induction varies with respect to time, ac losses appear in superconducting wires. The magnetic induction can be external or due to the current in the wire (self-field). The ac losses have two main consequences. On the one hand, they induce a temperature rise in the superconductor. Since the temperature margin is very small (< 1 K) for low-Tc materials (NbTi for example) such a rise can easily quench the superconducting coil, that is, destroy its superconductivity. On the other hand, ac losses are very expensive energetically, since they are dissipated at low temperatures. They therefore greatly reduce the advantage of using superconductors. From the second law of thermodynamics, the removal of energy at a cold temperature (Tc), requires work at a high temperature (T0), usually room temperature. For an ideal closed cycle the ratio of the minimum required work (Wmin) at T0 to the energy (Q) to be removed at Tc is given by Carnot’s expression

This depends mainly on the cold power and little on the cold temperature (Fig. 3, Ref. 9).

The ratio Wmin/Q in real conditions [Eq. (3)] is called the specific work, and its reciprocal the coefficient of performance. To calculate the cost of refrigeration, the losses at low temperature must be multiplied by the specific work. For an efficiency factor of 10%, it amounts to 740 W/W and 29 W/W for cold temperatures of 4

0.1

^ 100

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(D

Q_

tf)

W

1 1

ra

О

0.1

1

^ d K: 74

77 K:2.9

/

1

. 1

10 100 1000 Cold temperature Гс (K)

100

– | Nlllll| 1 ГІ1 1H[ 1 ТТГГІЧ 1

ТТПЇЇ1Г

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0 _______________________

M. 1 1

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Under development

…..

!»»■’■< ……… и

10

0.1 1 10 100 1000 104 10s 106 Cold power (W)

(a)

(to)

Fig. 3. (a) Carnot’s specific work and (b) efficiency factor as functions of the cold power (9).

K and 77 K, respectively. These two figures illustrate the advantage of operating at high temperatures from a cryogenic point of view and again underlines the interest in using HTSs. The ac loss cost is especially high for LTSs, and it must be reduced to an ultralow level for the system efficiency to be acceptable.

A simple way to understand the ac losses is to consider the Maxwell-Faraday law (curl E = — dB/dt). This shows that an electric field appears as soon as the magnetic induction varies with time. The induced electric field associated with a current density (transport current or persistent currents) results in losses. The losses per unit volume are the scalar product of these two vectors.

If it is not possible to suppress the ac losses, it is possible to reduce them by a suitable multifilament structure. This will depend on the field configuration (self-field, transverse or axial field), but ultralow-ac-loss superconducting strands are generally achieved with very fine twisted filaments embedded in a high-resistance matrix or with resistive barriers between filaments. The strand diameter should be low as well. Ac NbTi wires have small (< 0.2 mm) elementary strands with hundreds of thousands of filaments (< 0.2 ^m) in a CuNi resistive (0.4 /xQ-m) matrix (Fig. 2). The first NbTi low-ac-loss composites were developed only in the eighties when the technology for fine filament fabrication was sufficiently developed (10). Those strands have greatly extended the potential range for superconductivity (11). For high-Tc materials the requirements are less severe, since the cost of removing the ac-loss heat is reduced (29 W/W at 77 K compared to 740 W/W at 4 K). Nevertheless, no oxide superconducting tape actually fulfils them with present HTS wire technology.

The ac losses explain why superconducting devices are confined to applications with dc current and without or with time-varying fields, but in the latter case, protected from them.

IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS

If one starts with the basic ideal model for a sample-and-hold circuit, there are various ways to implement a switch and a capacitor in either discrete or monolithic forms. The interface between this model and the input signal or adjacent system blocks implies the usage of additional circuitry. There is also added complexity from dealing with different circuit nonideal­ities, an increase in operating speed, or a decrease in power consumption. The following subsections embrace this gradual approach from a basic model to a more complex structure, which provides an implementation that is close to real life. A variety of topologies and implementations is presented includ­ing open – and closed-loop, bipolar, and MOS-based, as well as current-mode circuits.

Open-Loop Sample-and-Hold Circuits

The simplest voltage-mode sample-and-hold circuit requires only two elements: a switch and a capacitor, as shown in Fig. 6 (1-3). The switch is controlled by a clock signal ф that is turned on and off each sample period. When the switch is on, the input voltage appears on the capacitor, and the circuit is actually in track mode. When the switch is turned off, the signal voltage at that instance is sampled on the capacitor, which holds the voltage constant until the next track phase. Although this ideally implements the desired sample-and – hold function using only two elements, the difficulty in realiz­ing an ideal switch severely limits the performance of such a design. Real switches are implemented using MOS or bipolar transistors or diode bridges, each of which has its own idio­syncrasies. This subsection will primarily focus on the use of MOS switches, while circuits utilizing bipolar transistors or diodes will be discussed in the following subsection.

A MOS transistor deviates from an ideal switch in several ways, the most obvious of which is in terms of on-resistance. When the MOS switch is turned on, it typically will have a low drain-to-source voltage (VDS) and a high gate-to-source voltage (Vos) [re-type MOS assuming (NMOS), opposite polar­ity for p-type MOS (PMOS)], causing it to operate in the tri – ode or nonsaturation region, where the drain-to-source cur­rent (Ids) is given by (4)

W

Another limitation of the MOS switch is charge injection and clock feedthrough, which are sometimes used inter­changeably to describe two effects that occur when the switch is turned off. When the transistor is on, charge collects under the gate of the transistor to form the channel from drain to source. When the switch is turned off, this charge exits the channel primarily to the drain and source, with the propor­tional split depending on speed of the clock transition and the impedance seen by the charge in each direction (6). The part of the charge that exits toward the sampling capacitor will cause the capacitor voltage to drop slightly (assuming an NMOS transistor with negative channel charge) from its im­mediately previous value. This would only create a constant pedestal error in the sample-and-hold circuit output if the packet of charge were always the same, but unfortunately this is not the case. The channel charge is approximately given by

: CoxWL(Vgs – Vt )

which reveals that, if the gate of the switch is tied to a con­stant supply voltage while turned on, then the channel charge will be signal dependent. In reality, this signal dependence of the injected charge is a major source of nonlinearity in the sample-and-hold circuit.

The second effect, often termed clock feedthrough, is caused by the MOS overlap capacitance between the gate and source or drain connected to the sampling capacitor. As the gate volt­age is dropping from a high on-voltage to a low off-voltage, the transistor actually shuts off when the gate is approximately a threshold voltage above the source or drain voltage. As the gate voltage continues to fall further, the voltage step is ca­pacitively coupled onto the sampling capacitor through the MOS overlap capacitance, causing the voltage on the sam­pling capacitor to change.

(W/L vs. 2W/L) of the series switch device

reduced by driving the gate with a bootstrapped version of the input signal, which makes the effects independent of signal to first order, just as in the case of switch on-resistance. The use of a full CMOS switch rather than only a single NMOS or a single PMOS device also gives a very rough cancellation of these effects. The NMOS device will inject negative channel charge onto the sampling capacitor, while the PMOS switch will inject positive channel charge. Similarly, the charge cou­pled through the overlap capacitances will also be in opposing directions. Unfortunately, these cancellations do not hold as the input is varied over its input range and so give little benefit.

Dummy-switch cancellation is another technique that can be used, though generally with limited effectiveness, to re­duce charge injection and clock feedthrough. As shown in Fig. 7, a dummy-switch device with half the gate area of the main switch is placed on the capacitor side of the sampling switch and is clocked with an inverted version of the sampling signal ф. Thus, during acquisition, the main switch is on and the dummy switch is off. At the sampling instant, the dummy switch is turned on, causing it to pull charge from the sam­pling capacitor to form the channel under its gate. This charge approximately cancels that injected by the main switch, assuming roughly half of the main switch charge was injected toward the capacitor.

IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS

The simple sample-and-hold circuit using a MOS switch can also experience input signal feedthrough during the hold mode due to the MOS overlap capacitances, especially when sampling high-speed inputs. When the circuit is in hold mode, the MOS gate will be pulled to the low supply voltage (assum­ing an NMOS switch), typically by a digital gate’s output. The digital gate will have a finite, nonzero resistance from its out­put to the low supply voltage, yielding an effective circuit such as that shown in Fig. 8. Analysis of this circuit reveals a nonzero transfer function from the input to the sampled output node, causing the feedthrough. Care must be taken during the design process to characterize the level of

feed­through that occurs and keep it sufficiently low through a low-resistance gate drive or more elaborate design modifica­tions.

IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS

Vin

(a) Basic schematic

IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS

(c) Hold mode, clock high

IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS

(b) Track (sample) mode, clock low

Figure 15. Sample-and-hold circuit where the hold­ing capacitor is connected in series between input and output; (a) detailed schematic with TN1, TN2, TP1, TP2 as switches, and input-output buffering; (b) sim­plified schematic during track mode; (c) simplified schematic during hold mode.

are n-p-n devices that function as series switches for steer­ing bias currents. Transistors TP1 and TP2 are p-n-p devices and work in either linear region or are turned off. For simplic­ity, it is assumed that the input and output buffers have unity gain. When the clock signal is low, transistor TN2 is turned off, and transistors TN1 and TN3 are turned on. Current I1 [generated by the current source as shown in Fig. 15(a)] flows entirely through resistor Rb1, which is designed such that the voltage drop on it, IRb1, turns off transistor TP1 (p-n-p type). Also, current I2 [generated by a current source as shown in Fig. 15(a)] flows through transistor TP2 (p-n-p type), which is biased in the linear region. Removing all transistors that are turned off, the schematic can be simplified as in Fig. 15(b). The voltage Vr2 shown on this figure can be expressed as

Vr2 = Vbe>TP2 + VR = VTln i? b2 (10)

1S, TP2 eTP2

where Vbe, TP2 is the base-emitter voltage of transistor TP2, VT is the thermal voltage, IS, TP2 is a constant current related to transistor TP2, and /8TP2 is the forward gain factor for transis­tor TP2. In other words, voltage Vr2 is independent of the in­put signal and is equal to the sum of the base-emitter voltage of transistor TP2 and the voltage drop across resistor Rb2. The voltage on the capacitor is V^ = Vin — Vr2, which is basically a shifted version of the input. The output voltage Vout is reset to Vr2 during this track or sample phase. When the clock sig­nal goes high transistors TN1 and TN3 turn off and TN2 turns on. Current I1 is steered to flow entirely through resis­tor Rb2, which is designed in a similar fashion as Rb1 such that the voltage drop on it, IRb2, turns off transistor TP2. The sche­matic, again, can be simplified as in Fig. 15(c). The input buffer provides some current Ib, which flows through transis­tor TP1 biasing it in the linear region. Vr1 can be also ex­pressed as in Eq. (10)

Vri = Vbe>TP1 + VB = VT ln jb – + —i? bl (11)

S, TP1 eTP1

with similar meanings applied to transistor TP1. The output voltage becomes

Vout = Vr1 – VChold I sampled = Vr1 + Vr2 – Vin I sampled (12)

It is worth mentioning that the output voltage holds a value of the input sampled when the clock goes high, and it is reset to Vr2 when the clock goes back to the low state. This puts an additional bandwidth requirement on the output buffer, which needs to settle more than the full range of the input signal. Also, assuming unity gain buffers, as stated initially, the output is a shifted version of the input taken with oppo­site sign. To achieve a perfect copy of the sampled input, a differential topology should be employed (to eliminate the shift) and either the input or output buffer should have a neg­ative gain. Since there is no true track mode at the output, one could consider the voltage on the capacitor as a function of the input when clock is low, and derive the equivalent ‘‘on’’ switch resistance. However, this requires taking into account

supply

Vin

Vo,

Clock

Figure 17. Diode-bridge-based sample-and-hold circuit with buff­ering and clamping to the output voltage.

IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS

kTLTLn

Ш

V,

supply

the design of the buffers and the parasitic effects of bipolar devices, which becomes rather involved.

The most common high-speed sample-and-hold circuits em­ploy semiconductor diode bridges. The switching times for semiconductor diodes are inversely proportional to the cutoff frequency characteristic to a given bipolar or bipolar CMOS process. Also the ‘‘on’’ resistance for these devices is very low compared to MOS-based switches. For a given current and reasonable sizes, the transconductance of bipolar transistors is significantly higher than that for their MOS counterparts. Since semiconductor diodes can be considered as bipolar de­vices with the base shorted to the collector, their ‘‘on’’ resis­tance is Rswitch = 1/gm = VT/I, where VT is the thermal voltage and I is the bias current flowing through the diode. The small ‘‘on’’ resistance and short switching times make the diode – bridge-based sample-and-hold circuits attractive for very – high-speed applications. Figure 16 presents such a basic sam – ple-and-hold circuit without input and output buffering. The switch is implemented using a diode bridge and two switched current sources. When the clock is low, the switched current sources do not generate any current and present a very high impedance at their output such that the diodes turn off

IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS

The voltage at nodes A and B during the track mode is input dependent. However, during hold mode these voltages change to some value independent of the input, and this change couples to the output node through the diode D2 and D3 junction capacitance, creating nonlinearity. This ef­fect can be virtually eliminated during the hold mode by clamping nodes A and B to a value dependent on the input sample. This creates a constant voltage change at these nodes from track to hold, and consequently, a constant perturbation of the held voltage, which results in offset but no nonlinearity. Figure 17 presents a circuit that performs the described clamping operation and includes input and output buffers that are assumed to have unity gain. When the clock signal is high, transistor T2 is turned off and current I2 flows through the diode bridge, generating a low-resistance path between the input and the holding capacitor Chold. This is the track mode when the voltage on Chold and the output voltage are following the input voltage. When the clock goes low, during the hold mode, transistor T1 turns off and transistor T2 turns on, bypassing the diode bridge. Current I3 is necessary to clamp the voltage at node B to Vin|sampled + VonD6. Meanwhile, node A is clamped to Vin|sampled — Von, D5. So the voltage at nodes A and B changes from track to hold by — Von, D1 — Von/D5 and Von, D3 + VonD6, respectively. These Von voltages are dependent on the diode sizes and bias current [Von = VT ln(Ib/IS)] so the coupling from nodes A and B to the voltage on Chold through the junction capacitance of diodes D2 and D3 is signal inde­pendent. Also, during the track mode diodes D5 and D6 are turned off since the output voltage follows the input and the voltages at node A and B are Vin + VonD1 and Vin — VonD4, re­spectively. It is important to note that the range of the input signal is limited to keep the diodes and current

It is worth mentioning that gm2 and gm1 are physically differ­ent elements and their mismatches as well as nonlinearity impact the performance of this sample-and-hold circuit. Also, the speed of the circuit depends largely on the operational amplifier settling time.

Real-life implementations of the current-mode sample-and – hold circuits described so far include usually more elaborate structures that are targeted at cancelling parasitic effects. Some of them employ differential topologies or improvements related to the finite output impedance of MOS transistors. Other structures employ more sophisticated clocking schemes or feedback to cancel charge-injection errors. Furthermore, closed-loop architectures must deal with stability issues that come into play as a trade-off regarding the accuracy (in the case of discrete-time feedback as in Fig. 28) or the speed (for the continuous-time feedback as in Fig. 29) of the circuit. Al­though there are advantages in using current-mode sample – and-hold circuits particularly regarding operating speed, their widespread usage was hampered by the need of voltage – to-current and current-to-voltage conversions as well as im­plementation difficulties when higher accuracy is required.

OPEN-CIRCUIT VOLTAGE

It should be noted that the vector effective height h is defined for the situation where the antenna is used for transmission. Let us consider how h is related to receiving antenna oper­ation.

Figure 3 shows two antenna systems in which antenna 1 with vector effective height h is used as a transmitted an­tenna in (a) and as a receiving antenna in (b). 101 is the termi­nal current and V01 is the open terminal voltage (open-circuit

voltage).

Antenna 2 is an infinitesimal dipole antenna with vector effective height hd = lz, which is used as receiving and trans­mitting antennas in (a) and (b), respectively.

The radiation field E1 from antenna 1 induces an open – circuit voltage at antenna 2

V02 — E1 ‘ ^Z

-jkR

= (-J 30 k—— IQ1h) • hd

Using Eq. (1), the radiation field from antenna 2 with termi­nal current 102 is written as

E2 — — j 30 k — /02hd

The open-circuit voltage V01 at antenna 1 induced by the radi­ation field from antenna 2 satisfies the relationship according to the [reciprocity theorem (1)]

^01I01 — V02I02

Substituting Eq. (4) into Eq. (6) yields

Пі = – j 30 k-

Using Eq. (5) and replacing V01 and E2 with V0 and Einc, re­spectively, Eq. (7) is written as

V0 — Einc • h

OPEN-CIRCUIT VOLTAGE

(a)

L

Г

02

Ant. 2, h

d

OPEN-CIRCUIT VOLTAGE

Figure 3. Determination of open-circuit voltage at antenna 1. (a) An­tenna 1 for transmission. Antenna 2 is an infinitesimal dipole for re­ception. (b) Antenna 1 for reception. Antenna 2 is an infinitesimal dipole antenna for transmission.

^ Ic:

OPEN-CIRCUIT VOLTAGE

Ant. 2, h

d

(b)

(9)

Equation (8) means that the open-circuit voltage is given by the inner product of the incident wave field and the antenna vector effective height.

Example. Let us obtain the maximum open-circuit voltage for a half-wavelength dipole antenna (L = A/2) located on the z axis. The maximum open circuit voltage is obtained when the polarization of an incident wave Einc is parallel to the di­pole; that is, the incident wave illuminates the dipole from the в = 90° direction. When the half-wavelength dipole has a current distribution of I(z’) = I0 cos kz’ over the antenna con­ductor from z’ = —A/4 to z’ = +A/4, Eq. (3) yields S = I0 A/wz using r • R = 0. Hence, h = A/wz. From Eq. (8), the maxi­mum open-circuit voltage is |V0| = |Einc|A/w.

EQUIVALENT CIRCUIT OF A RECEIVING ANTENNA

The original receiving antenna problem shown in Fig. 4(a) can be handled by superimposing two cases, shown in Fig. 4(b) and (c). In Fig. 4(b) an EM plane wave illuminating the an­tenna induces an open-circuit voltage of V0 = Einc • h. In Fig. 4(c) the antenna acts as a transmitting antenna with termi­nal current 1. Superimposing these two cases leads to a rela­tionship of

Vrec — V0 Vtrans

where Vrec = ZiI and Vtrans = ZAI, with ZA defined as the an­tenna input impedance. From Eq. (9), the terminal current 1

(15)

(16)

I

I

Vre ^inc

+

-V

Einc

Z

+

L

+

Vn

Vtrans

|E. • h|2

w = L = w

L 4 r L max

|E. • h|2 |E. • h|2

‘ inc ^ * inc ^

E 4(-^а+га) 4Rl

(a)

I =

(11)

(12)

(b)

Figure 4. A receiving antenna. (a) Original receiving antenna prob­lem. (b) Antenna with open terminals. (c) Transmitting antenna.

is given as

V0

(10)

Za + Zt

Therefore, the equivalent circuit for Eq. (10) is as shown in Fig. 5, where the open-circuit voltage V0 is used as a voltage generator with an internal impedance ZA.

Let us express the load impedance ZL and the antenna in­put impedance ZA as

ZL – RL + jXL

ZA – (RA + rA) + jXA

It follows that half of the power provided by the generator is delivered to the antenna load. Note that WLmax in Eq. (15) is the maximum power that can be delivered to the load ZL, be­cause the antenna is perfectly matched to the load. Also, note that WR is recognized as the scattered (reradiated) power from the receiving antenna (1,4,5).

Example. The relationship WR = WL obtained when the im­pedance is matched can be checked by a numerical technique called the method of moments (3), where the incident power Winc and the received power WL are calculated. The scattered power is obtained from Winc — WL. For a center-load dipole antenna (4), the relationship WR = WL is obtained when the antenna length L is less than 0.8A. Limits on the validity of the equivalent circuit shown in Fig. 5 are discussed else­where (1,4,5).

RECEIVING CROSS-SECTION AND APERTURE EFFICIENCY

The receiving cross-section Ar of an antenna is defined as the ratio of the power WL [Eq. (13)] received by the antenna to the Poynting power (power density of the incident wave, Pn = |EiJ2/Zo, where Zo = 120Ш):

_|Emc. h|2RL Z0 r lzA +ZLI2 |Emc|2

where Ra and rA are the radiation resistance and the loss re­sistance (not contributing to the radiation), respectively. Then, the power delivered to the antenna load is given as

Ar =

(17)

Using an impedance mismatch factor Mimp defined as WL WLmaxMimp, Eq. (17) is rewritten as

V0|2 Rl

(13)

|ZA + ZL|2

and the power consumed in the generator is given as

|V0|2(RA+rA)

A Iza+zlI2

l^nc-bl2 M 4 (RA+rA)

Zn

Ar –

|Eind2

zo

|Eincl2

(18)

.|Einc • h|2

Mm

4R«

(14)

where Rl = Ra + rA = Ra/^ (Appendix Eq. (a1)) is used. Using the absolute gain Ga [see Eq. (a5)], Eq. (18) is written as

When an impedance matching condition is satisfied [i. e., when Zl is complex conjugate of Za(Rl = RA + rA and XL =

= AlG lE-nc-hl2 r 4я a |Emc|2|h|2

Mim

(19)

Because the received power is proportional to the square of the open-circuit voltage, that is, |Einc • h|2, the third factor |Einc • h|2/|Einc|2|h|2 in Eq. (19), is the reduction factor of the re­ceived power from polarization mismatch. Let the third factor be denoted as Mpoi, which has a maximum value of 1 for the case in which h is a real constant multiplied by the complex conjugate of Einc. Eq. (19) now can be written as

OPEN-CIRCUIT VOLTAGE

Ar = t— GMM

(20)

a pol imp

4n

The maximum receiving cross-section, which is called the ef­fective area Aeff, is obtained when Mpol = Mimp = 1.

^eff – 4jr Ga

(21)

ation power density from a reference antenna that has the same input power as the test antenna:

G(e^) —

(a4)

W

Z

W

Ga — nD

Let the receiving antenna gain be defined as the ratio of the effective area of the antenna, Aeff, to the effective area of an isotropic antenna, Aeff iso = A2/4w. Then, from Eq. (21), the re­ceiving antenna gain is equal to the absolute gain when the same antenna is used as a transmitting antenna.

Example. An isotropic antenna has a gain of Ga = 1 (=0 dB) by definition. Using Eq. (21), the effective area is calculated to be Aeff = 0.0796A2. An infinitesimal dipole, whose vector effective height is |h| = l|sin в|, has a gain of Ga = 1.5 ( = 1.76 dB) at в = 90° and an effective area of Aeff = 0.119A2. A half­wavelength dipole antenna with |h| = A/w yields an effective area of 0.130A2, because Ga = 1.64 (=2.15 dB). Note that all Gas are calculated using Appendix (a6) and (a7) with ^ = 1.

When a receiving antenna has an aperture Aap which is much larger than the wavelength A, the performance of the receiving antenna is evaluated by how efficiently the aperture is utilized for reception. Since the receiving antenna of Aap has the potential to collect an EM wave power of Wap = PincAap, the ratio of the received power PincAeff to Wap is defined as the aperture efficiency ^ap, where

where E0 is the far-field radiated from the reference antenna, and Win, 0 is the power input to the reference antenna. Note that the maximum value of the gain is conventionally used for the antenna gain if the coordinates (в, ф) for the direction of interest are not specified.

When an isotropic antenna (hypothetical antenna radiat­ing with uniform radiation power density in all directions) is chosen as the reference antenna, the gain is called the abso­lute gain and denoted as Ga. Equation (a4) becomes

|E(R, 9, 0)|2/Win |E0I2/Wln>0

4nR2 |E(R, Є, ф)^

Ga =

(a5)

(a6)

— n

Zn

Using Eq. (1) and Eq. (a2),

4nR2 |E(R, Є, ф)^

rad

Advanced Guidance Algorithms

Classic PNG and APNG were initially based on intu­ition. Modern or advanced guidance algorithms exploit op­timal control theory, i. e. optimizing a performance mea­sure subject to dynamic constraints. Even simple opti­mal control formulations of a missile-target engagement (e. g., quadratic acceleration measures) lead to a nonlinear two-point boundary value problem requiring creative so­lution techniques, e. g., approximate solutions to the asso­ciated Hamilton-Jacobi-Bellman equation—a formidable nonlinear partial differential equation (23). Such a formu­lation remains somewhat intractable given today’s comput­ing power, even for command guidance implementations that can exploit powerful remotely situated computers. As a result, researchers have sought alternative approaches to design advanced (near-optimal) guidance laws. In Ref­erence 20, the authors present a PNG-like control law that optimizes square-integral acceleration subject to zero miss distance in the presence of a one pole guidance-control – seeker system.

Even for advanced guidance algorithms (e. g., optimal guidance methods), the effects of guidance and control sys­tem parasitics must be carefully evaluated to ensure nom­inal performance and robustness (20). Advanced (optimal)

In contrast with PNG, this expression shows that the re­sulting APNG acceleration requirements decrease with time rather than increase. From the expression, it fol­lows that increasing N increases the initial acceleration requirement but also reduces the time required for the acceleration requirements to decrease to negligible lev­els. For N — 4, the maximum acceleration requirement

for APNG, acAPNGmax — — Nat, is equal to that for PNG,

-]at. For large N — 5, APNG requires a

acA png(,) — 2 N

N2

N

it can be shown (under the simplifying assumptions given earlier) that

Variants of PNG

Within Reference 20, the authors compare PNG, APNG, and optimal guidance (OG). The zero miss distance (sta­bility) properties of PPNG are discussed within Reference 24. A nonlinear PPNG formulation for maneuvering tar­gets is provided in Reference 27. Closed form expressions for PPNG are presented in Reference 28. A more complex version of PNG that is “quasi-optimal” for large maneu­vers (but requires tgo estimates) is discussed in Reference 29. Two-dimensional miss distance analysis is conducted in Reference 21 for a guidance law that combines PNG and pursuit guidance. Within Reference 30, the authors extend PNG by using an outer LOS rate loop to control the ter­minal geometry of the engagement (e. g., approach angle). Generalized PNG, in which acceleration commands are is­sued normal to the LOS with a bias angle, is addressed in Reference 31. Three-dimensional (3D) generalized PNG is addressed within Reference 32 using a spherical coor­dinate system fixed to the missile to better accommodate the spherical nature of seeker measurements. Analytical solutions are presented without linearization. Generalized guidance schemes are presented in Reference 33, which re­sult in missile acceleration commands rotating the missile perpendicular to a chosen (generalized) direction. When this direction is appropriately selected, standard laws re­sult. Time-energy performance criteria are also examined. Capturability issues for variants of PNG are addressed in Reference 34 and the references therein. Within Reference 35, the authors present a 2-D framework that shows that many developed guidance laws are special cases of a gen­eral law. The 3-D case, using polar coordinates, is consid­ered in Reference 36.

SUPERCONDUCTING MOTORS, GENERATORS, AND ALTERNATORS

Superconductors are very promising and exciting materials for electric power engineering in general and for electric machines in particular. By allowing very high current densities and by suppressing the Joule losses, superconductors improve the performance of electric machines by reducing weight, improving efficiency and, to a lesser degree, by increasing compactness. The reduction of losses results in long-term savings in capital cost, making superconducting machines attractive from an economic point of view. Since a cryogenic system is required to maintain the superconducting state, these advantages appear only above a critical (breakeven) size or rating, such that where the refrigeration penalty is negligible. Superconductivity is thus attractive only for large electrical machines. Small motors (up to a few kilowatts) will not be superconducting except if room-temperature superconductors are discovered, which is highly improbable.

The critical size is reduced when the operating temperature increases. Devices with high-critical – temperature superconductors will be attractive for lower ratings than systems cooled with liquid helium.

Electric Machines—General Structure(l)

An electric machine is reversible. It can operate as a motor, converting electrical into mechanical power, or as a generator, converting mechanical input into electricity. The electromagnetic force or torque is produced in two ways. The first one is the interaction between currents, called armature currents, and a variable-reluctance structure (variable-reluctance machines). The second and more widely used way is the interaction between currents and a magnetic field called the excitation field. The mobile part can be either the armature or the excitation. But as the energy transfer to a moving part creates losses except by electromagnetic way, the armature is preferably stationary.

The torque per unit volume is proportional to the excitation field component perpendicular to the current times the armature ampere-turn loading, as shown below. The armature ampere-turn loading is the total armature current divided by the mean armature circumference. The expression for the maximum torque (rmax) for a three-phase machine is simply:

where

Bo = excitation field component K = armature ampere turn loading ro = mean armature radius L = active length Ns = total series turns per phase kd = winding factor

I = rated armature current

#mach = approximate machine volume

лі*h кг iWh

The excitation field is created either by permanent magnets or by current flow in a winding. Permanent magnets are limited in magnetic induction and are made of very expensive materials, but they are not dissi­pative. They are well suited particularly for small machines (kilowatt range). The currents in a conventional conductor produce heat through the Joule effect (R i2 where R is the resistance and i the current), dissipating energy. The current capacity is hence limited by the ability to remove heat. Better cooling conditions increase the current capacity but reduce the efficiency. The current density (current per unit cross-sectional area) is then limited by thermal and economic factors. The allowable current density in copper is on the order of amperes per square millimeter (5 MA/m2 to 10 MA/m2). With such values the amounts of conductor required to produce magnetic fields without magnetic materials are large, leading to huge Joule losses. Thanks to the peculiar properties of soft magnetic materials (high relative permeability), the total current (ampere turns) required to produce a given magnetic induction is greatly reduced. For this reason practically all electric machines have a magnetic circuit with slots where the windings are embedded.

The armature ampere-turn loading is limited by Joule losses and by the current density allowable in the conductors, because the space they can occupy is limited.

The magnetic circuit has other advantages than the reduction ofthe excitation current. It confines the flux within the machine and reduces the stray field to negligible levels. It also prevents magnetic disturbances to other equipment. The magnetic circuit is also very useful from a mechanical point of view. When the conductors are inserted into slots they are subjected only to a reduced electromagnetic force, since the field concentrates itself in the teeth. The electromagnetic force is mainly applied at the interface between the slots and the magnetic teeth. The torque is then essentially supported by the magnetic circuit and not by the conductors. The reduced mechanical stresses on the conductors are an important advantage, because the mechanical strength of copper is low. In a slotted structure, no special care need be taken in order to reduce the eddy-current losses in the conductors, since they only see low fields. Without magnetic teeth, a strong mechanical support structure must be provided in order to sustain all the electromagnetic torque, and the conductors should follow the finely divided Litz wire configuration to avoid large eddy-current losses. However, the magnetic circuit is heavy, the increased magnetic induction it provides is limited by saturation, and it creates pulsating torques, because the alternation of magnetic teeth and slots produces local magnetic variations. The magnetic teeth also reduce the space available for conductors and thus the armature ampere-turn loading. The slotted structure is also not convenient for insulation, so that the maximum voltage is limited (to about 30 kV).

Superconducting materials show promise for electric machines because they offer the possibility to in­crease both the excitation field and the armature ampere-turn loading (2,3). Superconductors are particularly convenient for producing magnetic fields that are constant in time. Since the current densities in superconduc­tors can be very high (up to a hundred times the allowable value in copper, i. e., hundreds of megamperes per square meter), the required quantity of conductor to produce a given field is greatly reduced from that with conventional conductors, even without the help of magnetic materials. The magnetic circuit is usually nearly removed when using superconductors. Magnetic materials are in general used only to form a magnetic shield in order to avoid large stray fields outside the machine. Current maintenance in a superconducting winding does not cost any energy, due to the absence of losses for constant current and constant external field. The disappearance or large reduction of the magnetic circuit leads to a light and saturation-free structure with

Fig. 1. Schematic cross sections of ac generators. (a) classical; (b) superconducting field winding; (c) fully superconducting.

more active space for conductors and insulation materials. The ampere-turn loading and the voltage can then be increased. The absence of iron teeth will decrease vibration by suppressing torque ripples. Acoustically very quiet electric machines can be designed.

However, the torque is applied directly to the conductors. They must therefore be supported by a suitable structure. An armature without magnetic teeth subjects the conductors to large forces at twice the frequency of rotation, which must be restrained by novel means of support for which high reliability must be main­tained. Figure 1 shows the main differences between a conventional machine and superconducting ones (for synchronous machines).

The weak point of a conventional machine is in general its insulation, which degrades badly with time. It is very sensitive to thermal cycling, and overheating strongly affects its lifetime. A cryogenic system is hence very favorable from this point of view: it almost completely avoids thermal cycling in operation. Moreover, at low temperatures all aging process are slowed down. The cryogenic components of superconducting machines should thus last longer, particularly if the machine remains at low temperature. Numerous thermal cycles from room temperature to cryogenic temperature must be avoided. Furthermore, they are costly in time and energy.

The very high current densities in superconductors make them very attractive for the armature by increasing the ampere-turn loading. However, the armature currents are in general alternating, so that losses appear in the superconductors. This is an important disadvantage in a cryogenic environment. In order to

Bi-2223 PIT 3.5 x 0.35 mm2 (BICC) 36 Bi-2233 filaments. Ag matrix

Fig. 2. Engineering critical characteristics of superconducting materials and wire cross sections.

discuss this point and for the sake of completeness, some information about superconducting wires (materials and ac losses) will be given in the following sections.